/******************************************************************************
* (C) Copyright 2009 <Company Name> All Rights Reserved
*
* MODULE:    name
* DEVICE:     
* PROJECT:   
* AUTHOR:    vqa   
* DATE:      2011 6:57:26 PM
*
* ABSTRACT:  You can customize the file content form Templates "verilog File"
*            
*******************************************************************************/

module register_bank (
        input clk,
        input rst_n,
	
        input [1:0] address,
        input read,
        input write,
        input chipselect,
        input [3:0] byteenable,
        input [31:0] writedata,
	
        output [1:0] address_out_sniffer,
        output read_out_sniffer,
        output write_out_sniffer,
        output [31:0] writedata_out_sniffer,
        output chipselect_out_sniffer,
	
        output logic [31:0] readdata
    );

    assign address_out_sniffer = address;
    assign read_out_sniffer = read;
    assign write_out_sniffer = write;
    assign writedata_out_sniffer = writedata;
    assign chipselect_out_sniffer = chipselect;

    logic [31:0] reg1, reg2, reg3, reg4;
    
    
    
    always_ff @(posedge clk)
    begin
        if(!rst_n)
        begin
            reg1 <= 0;
            reg2 <= 0;
            reg3 <= 0;
            reg4 <= 0;
        end
        else if(chipselect)
        begin
            if(write)
            begin
                case(address)
                    0:
                    reg1 <= writedata;
                    1:
                    reg2 <= writedata;
                    2:
                    reg3 <= writedata;
                    3:
                    reg4 <= writedata;
                    default:
                    begin
                        //nada
                    end
                endcase
            end
            else if(read)
            begin
                case(address)
                    0:
                    readdata <= reg1;
                    1:
                    readdata <= reg2;
                    2:
                    readdata <= reg3;
                    3:
                    readdata <= reg4;
                    default:
                    readdata <= 0;
                endcase
            end
        end
    end
endmodule


/******************************************************************************
*
* REVISION HISTORY:
*    
*******************************************************************************/
